1. Field of the Invention
The present invention relates to a three-state complementary field effect integrated circuit and, more particularly, to a three-state complementary field effect integrated circuit comprising an output circuit comprising a series connection of two field effect devices having conductivity types different from each other.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a part of conventional computer system in which, for example, a clock signal is provided from a CPU (Central Processing Unit) to its peripheral circuit. Referring to FIG. 1, a CPU 51 outputs a clock signal cl from a clock output terminal 52 and applies the same to a clock input terminal 55 of a peripheral circuit 54 through an inverter 53. The inverter 53 is a driver circuit for relaying the clock signal cl.
The inverter 53 shown in FIG. 1 is an example of application example of the present invention. Such an inverter is often used as an output circuit for relaying a digital circuit and, in general, operates to receive an input signal having two values and output an output signal having two values.
FIG. 2 is a schematic diagram of an inverter circuit of one example of an output circuit of a conventional CMOS (Complementary Metal Oxide Semiconductor) integrated circuit. The inverter circuit shown in FIG. 2 comprises a series connection of a p type MOS transistor P1 and an n type MOS transistor N1 connected between a terminal 3 of the power, supply Vcc and a terminal 4 of the ground GND. Each of gates of the transistor P1 and the transistor N1 is connected together to an input terminal 13 and a node of the transistor P1 and the transistor N1 constitutes an output terminal 2.
An operation is described. When an input voltage of the level of the ground GND (referred to as L level hereinafter) is applied to the input terminal 13, the transistor P1 turns on and the transistor N1 turns off, with the result that the output terminal 2 is brought to the output voltage of the level of the power supply Vcc (referred to as H level hereinafter). On the contrary, when the input voltage of H level is applied to the input terminal 13, the transistor N1 turns on and the transistor P1 turns off, with the result that the output terminal 2 is brought to the output voltage of L level. When the input voltage applied to the input terminal 13 is at a medium value between H level and L level, both transistors P1 and N1 turn on and a voltage determined by the ratio of an on resistance of the transistor P1 to that of the transistor N1 is outputted from the output terminal 2.
FIG. 3 is a schematic diagram showing an equivalent circuit when the output circuit shown in FIG. 2 is mounted on a printed circuit board. Referring to FIG. 3, an inductance Ll is formed in a connection between the power supply terminal 3 and an external power supply Vcco terminal 19 for receiving the power supply from outside the board and an inductance L2 is formed in connection between the ground terminal 4 and an external ground GNDo terminal 20 for grounding outside the board, both inductance components being formed by an influence from a frame and a gold wire of the integrated circuit and from a wire in the printed circuit board.
Recently, with a demand for a higher speed of operation of the integrated circuit, a current output capacitance (driving capability) of the field effect integrated circuit constituting the output circuit is increased. For example, a certain integrated circuit has an output short-circuit current of 200mA to 300mA under a supply voltage of 5V. An increase of the current output capacitance in the integrated circuit causes an increase of a through current flowing between the power supply and the ground when the output voltage changes, that is, an increase of unnecessary power consumption.
Referring to the equivalent circuit of the output circuit shown in FIG. 3, a spike voltage Vs generated, when the output voltage of the output circuit changes, at the inductance L1 or L2 is represented by ##EQU1## where I is a current flowing into the inductance L1 or L2 and t is a time. Therefore, it follows that the above-mentioned increase in the through current in the output circuit causes an increase in the spike voltage Vs generated at the inductances L1 and L2.
FIG. 4 is a schematic waveform diagram showing a voltage waveform outputted from the output terminal 2 of the equivalent circuit of the output circuit shown in FIG. 3. Referring to the waveform diagram shown in FIG. 4, the ordinate denotes a voltage value of the output and the abscissa denotes the lapse of time. Reference characters V.sub.OH and V.sub.OL denote voltages of H level and L level outputted from the output terminal 2, respectively. The waveform diagram shown in FIG. 4 denotes that the output voltage includes the spike voltage when the output voltage of the output circuit changes.
There is another problem that this spike voltage, in other words, a spike noise causes malfunction of another circuits connected to this output circuit or existing near this output circuit.
A prior art of interest to a three-state complementary field effect integrated circuit in accordance with the present invention is disclosed in Japanese Patent Laying-Open Gazette No. 48616/1985, entitled "Logic Circuit". This prior art comprises an output pre-stage circuit comprising a composite gate, and the pre-stage circuit enables the output circuit to have three output states in response to an control signal.